Verification techniques for system-level design
(eBook)
Author
Contributors
Published
Amsterdam ; Boston : Morgan Kaufmann Publishers, ©2008.
ISBN
9780080553139, 0080553133, 1281049646, 9781281049643, 9786611049645, 6611049649
Physical Desc
1 online resource (viii, 240 pages) : illustrations
Status
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Format
eBook
Language
English
Notes
Bibliography
Includes bibliographical references and index.
Description
This book will explain how to verify SoC logic designs using formal and semi-formal verification techniques. The critical issue to be addressed is whether the functionality of the design is the one that the designers intended. Simulation has been used for checking the correctness of SoC designs (as in functional verification), but many subtle design errors cannot be caught by simulation. Recently, formal verification, giving mathematical proof of the correctness of designs, has been getting much more attention. So far, most of the books on formal verification target the register transfer level (RTL) or lower levels of design. For higher design productivity, it is essential to debug designs as early as possible. That is, designs should be completely verified at very abstracted design levels (higher than RTL). This book covers all aspects of high-level formal and semi-formal verification techniques for system level designs. First book that covers all aspects of formal and semi-formal, high-level (higher than RTL) design verification targeting SoC designs. Formal verification of high-level designs (RTL or higher). Verification techniques are discussed with associated system-level design methodology.
Description
Printbegrænsninger: Der kan printes kapitelvis.
Language
English.
Local note
O'Reilly,O'Reilly Online Learning Platform: Academic Edition (EZproxy Access)
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Citations
APA Citation, 7th Edition (style guide)
Fujita, M., Ghosh, I., & Prasad, M. (2008). Verification techniques for system-level design . Morgan Kaufmann Publishers.
Chicago / Turabian - Author Date Citation, 17th Edition (style guide)Fujita, Masahiro, 1956-, Indradeep Ghosh and Mukul. Prasad. 2008. Verification Techniques for System-level Design. Morgan Kaufmann Publishers.
Chicago / Turabian - Humanities (Notes and Bibliography) Citation, 17th Edition (style guide)Fujita, Masahiro, 1956-, Indradeep Ghosh and Mukul. Prasad. Verification Techniques for System-level Design Morgan Kaufmann Publishers, 2008.
MLA Citation, 9th Edition (style guide)Fujita, Masahiro, Indradeep Ghosh, and Mukul Prasad. Verification Techniques for System-level Design Morgan Kaufmann Publishers, 2008.
Note! Citations contain only title, author, edition, publisher, and year published. Citations should be used as a guideline and should be double checked for accuracy. Citation formats are based on standards as of August 2021.